Ultra Low Power Analog Integrated Circuits Beyond CMOS

The book would provide an in-depth analysis of the latest developments and innovations in the field of ultra low power analog integrated circuits. The book would start by introducing the concept of low power consumption and energy harvesting, and how it is becoming increasingly important in the era of the Internet of Things (IoT) and wearable devices.

It would then cover various topics such as body biasing, threshold voltage tuning, subthreshold circuits, and tunneling FETs, and how they are used to achieve low power operation. The book would also delve into the use of new materials and device structures, such as MEMS-based devices, carbon nanotube FETs, graphene FETs, spin FETs, ambipolar transistors, and biologically inspired circuits.

Additionally, the book would explore the challenges posed by hybrid analog-digital circuits and low voltage operation, and provide techniques for analog power gating, low voltage data converters, and on-chip energy storage. The book would also provide guidance on the design and implementation of non-volatile analog circuits and hybrid CMOS-memristor circuits.

The book would be aimed at electrical engineers, integrated circuit designers, and researchers in the field of low power analog integrated circuits. The book would provide a comprehensive and cutting-edge approach to ultra low power analog integrated circuits, equipping readers with the knowledge and skills necessary to tackle the latest challenges and innovations in the field.

Analog circuit design is going in the direction of Low Voltage and Low Power application

requirements of portable devices like mobiles, laptops, pacemakers, etc. As the fabrication

technology scaling continues, the supply voltage must be reduced to reduce electric field across the

channel to prevent oxide breakdown .

However, this pattern brings additional disadvantages, as downscaled process node endures the

random fluctuation of process parameters, voltage and temperature sensitivity (PVT) . The

dimensions of the recent transistors are so low that it is now become challenging to prevent many

issues such as scattering effect, decreased gate control over drain current (ID), parasitics,

random dopant fluctuation, channel mobility, lithographic limitations, the threshold voltage (VTH)

variability, drain to source tunneling, increased heat production and increased gate oxide as

well as junction leakage, etc.

The minimum supply voltage (VDD) in CMOS is much higher at nanometer technology node. With the

requirement of highly down-scaled transistors in state-of-the- art ICs, lower power consumption,

high performance and battery-operated systems, at nanometer technology node, CMOS faces many short

channel effects (SCEs) like Drain Induced Barrier Lowering (DIBL), Gate Induced Drain Leakage

(GIDL), process variations, etc., because of which the maximum usable frequency is reduced